1. Field of the Invention
The invention relates to a chopper comparator. and an A/D converter.
2. Description of the Related Art
In a recent stream of a system-on-silicon due to a progress of formation of a fine pattern of a semiconductor process, a demand to assemble a high-speed A/D converter into a large scale integrated circuit (LSI) is increasing. Even in what is called a high-speed A/D converter, however, its conversion frequency varies in a range from several MHz to tens of MHz in accordance with a use object. As such a high-speed A/D converter, there have been known a flash type A/D converter for converting an inputted analog signal to digital signals of n bits in parallel, a 2-step flash type A/D converter for divisionally converting an inputted analog signal at two stages of upper bits and lower bits, and the like.
FIG. 1 is a circuit diagram showing a conventional chopper comparator which is used in a conventional flash type or 2-step flash type A/D converter.
As shown in FIG. 1, the conventional chopper comparator has: an input terminal 101 for an analog input voltage V.sub.IN ; an input terminal 102 for a reference voltage V.sub.ref ; CMOS inverters 103 to 105 of three stages; an output terminal 106 for an output voltage V.sub.OUT ; capacitors C.sub.1 ' and C.sub.2 '; and switches SW1' to SW4' constructed by CMOS analog switches. The input terminals 101 and 102 are connected to one end of the capacitor C.sub.1 ' through the switches SW1' and SW2'. The other end of the capacitor C.sub.1 ' is connected to an input terminal of the CMOS inverter 103. An output terminal of the CMOS inverter 103 is connected to an input terminal of the CMOS inverter 104 through the capacitor C.sub.2 '. The input and output terminals of the CMOS inverter 103 are connected through the switch SW3'. Similarly, input and output terminals of the CMOS inverter 104 are connected through the switch SW4'. The output terminal of the CMOS inverter 104 is connected to an input terminal of the CMOS inverter 105. An output terminal of the CMOS inverter 105 is connected to the output terminal 106 for the output voltage V.sub.OUT.
Reference numeral 107 denotes a power source for supplying a power voltage V.sub.DD and 108 denotes a power source for supplying a power voltage V.sub.SS. Reference characters Q.sub.101 to Q.sub.106 denote transistors constructing the CMOS inverters 103 to 105. In this case, the transistors Q.sub.101, Q.sub.103, and Q.sub.105 are p-channel MOSFETs as load transistors and the transistors Q.sub.102, Q.sub.104, and Q.sub.106 are n-channel MOSFETs as driver transistors.
Reference characters Q.sub.107 to Q.sub.114 indicate transistors constructing the switches SW1' to SW4'. A clock signal CK or an inverted clock signal CK is supplied to the transistors Q.sub.107 to Q.sub.141, thereby controlling the ON/OFF operations of the switches SW1' to SW4'. In this case, the switches SW1', SW3', and SW4' are turned on for a period of time during which the clock signal CK is at the high level and are turned off for a period of time during which the clock signal CK is at the low level. On the other hand, the switch SW2' is turned on for a period of time during which the clock signal CK is at the low level and is turned off for a period of time of the high level.
The operation of the conventional chopper comparator constructed as mentioned above will now be described.
That is, in the chopper comparator, when the clock signal CK is set to the high level, the switches SW1', SW3', and SW4' are turned on and the switch SW2' is turned off. For this period, the analog input voltage V.sub.IN from the input terminal 101 is supplied to the capacitor C.sub.1 ' and is sampled and a self-offset cancellation of the CMOS inverters 103 and 104 is performed. For this sampling period, in principle, predetermined operation currents I.sub.1 ' to I.sub.3 ' flow into the CMOS inverters 103 to 105. When electric potentials at the input and output terminals of the CMOS inverters 103 to 105 are equal, the operation currents I.sub.1 ' to I.sub.3 ' at this time correspond to DC currents which flow into the CMOS inverters 103 to 105.
Subsequently, when the clock signal CK is set to the low level, the switches SW1', SW3', and SW4' are turned off and the switch SW2' is turned on. For this period, the reference voltage V.sub.ref from the input terminal 102 is supplied to the capacitor C1', so that a level of the analog input voltage V.sub.IN which was sampled before is compared with that of the reference voltage V.sub.ref. The voltage which is applied to the capacitor C.sub.1 ' at this time is inverted by the CMOS inverter 103. Further, an output of the CMOS inverter 103 is amplified by the CMOS inverters 104 and 105 and is generated as an output voltage V.sub.OUT from the output terminal 106. In this case, when V.sub.IN .gtoreq.V.sub.ref, the output voltage V.sub.OUT corresponding to "1" is generated and, when V.sub.IN &lt;V.sub.ref, the output voltage V.sub.OUT corresponding to "0" is generated. For this comparing period of time, the operation currents I.sub.1 ' to I.sub.3 ' of the CMOS inverter 103 to 105 are equal to almost 0.
Hereinafter, the above-mentioned sampling operation and comparing operation are repeated in response to the clock signal CK.
FIGS. 2A and 2B are schematic diagrams showing a current consumption in association with the operation of the conventional chopper comparator. In this instance, FIG. 2A shows a waveform of the clock signal CK and FIG. 2B shows a waveform of the consumed current. In the conventional chopper comparator, any current is hardly consumed except for the operation currents I.sub.1 ' to I.sub.3 ' of the CMOS inverters 103 to 105. Therefore, as shown in FIG. 10, the current consumption of the conventional chopper comparator is equal to (I.sub.1 '+I.sub.2 '+I.sub.3 ') which is the total amount of the operation currents I.sub.1 ' to I.sub.3 ' of the CMOS inverters 103 to 105.
The n-bit flash type A/D converter is constructed by using the (2.sup.n -1) foregoing conventional chopper comparators. The n-bit 2-step flash type A/D converter is constructed by using the (2.sup.n/2 -1)+2(2.sup.n/2 -1+a): where, (a) denotes the number of correction bits! foregoing conventional chopper comparators. Specifically speaking, for example, in case of an A/D converter of 8-bit 2-step flash type for video, the total number of chopper comparators is equal to 57 (where, the number (a) of correction bits assumes 3).
In the conventional chopper comparator, ordinarily, as the operation currents I.sub.1 ' to I.sub.3 ' of the CMOS inverters 103 to 105 are larger, namely, as the current consumption is larger, gains of the CMOS inverters 103 to 105 increase. On the other hand, the gains of the CMOS inverters 103 to 105 decide a conversion speed of the chopper comparator. Consequently, in the conventional chopper comparator, when the conversion speed is determined, the current consumption is naturally decided.
However, the conventional A/D converter constructed by using a number of conventional chopper comparators as mentioned above has the following problem.
That is, when it is required that the A/D converter operates at a low electric power consumption, it is indispensable to reduce the current consumption of the sole chopper comparator. As a method of coping with such a situation, there is a general method of reducing a ratio W/L of a gate width W to a gate length L of each of the transistors Q.sub.101 to Q.sub.106 constructing the CMOS inverters 103 to 105 in the above-mentioned conventional chopper comparator shown in FIG. 1.
On the other hand, the gain of each of the CMOS inverters 103 to 105 is decided by a ratio W/L of the gate width W to the gate length L of each of the transistors Q.sub.101 to Q.sub.106. Therefore, ordinarily, the ratio W/L of the gate width W to the gate length L of each of the transistors Q.sub.101 to Q.sub.106 constructing the CMOS inverters 103 to 105 is decided in accordance with the conversion speed which is required for the chopper comparator, so that the current consumption of the chopper comparator is also determined. Consequently, in order to realize a proper conversion speed, it is the best method that the ratio W/L of the gate width W to the gate length L of each of the transistors Q.sub.101 to Q.sub.106 constructing the CMOS inverters 103 to 105 is optimized. However, since it is impossible to meet all of requests for various conversion speeds, there is a problem such that as an actual countermeasure, in many cases, a high speed A/D converter which can cover from several MHz to tens of MHz is used under a sacrifice of the current consumption.